The invention relates to a circuit configuration for the generation of clock signals for a semiconductor memory that are edge-synchronous with the output signals of a clock generator, comprising an input stage to which the output signals of the clock generator are applied, a phase detector which receives the signals output by the input stage and whose output signals control a voltage-controlled oscillator which supplies the clock signals for the semiconductor memory, and a conversion stage which applies signals related to the output signals of the oscillator to the phase detector, that controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage and the signals also reaching it from the conversion stage becomes zero.
The essential components found on the motherboard of modern computers, apart from the processor (CPU), also comprise, among others, a clock generator which supplies all the clock signals required for the control of the component units. It is especially important for the coordinated operation of the processor and the semiconductor memories, which constitute the main memory, that both the processor and the main memory are controlled with as much edge-synchronization as possible by the corresponding clock signals. Only when this condition is fulfilled, can the correct processing of data as well as the correct interchange of data be guaranteed.
Since the voltage values of the clock generator output signals cannot be used directly for the control of the semiconductor memory components, constituting the main memory, these output signals are usually applied to the main memory via a PLL circuit, thus ensuring that these output signals are converted to the correct driving levels. The PLL circuit is the cause of a certain delay of the signals output by it with respect to the clock generator output signals reaching it. For a given voltage value of the clock generator output signals, the circuit can be optimized in such a way that the time delay due to the PLL circuit can still be tolerated and thus does not contribute to the deterioration of the data transfer process between the processor and the main memory.
The clock generators of modern motherboards are, however, conceived in such a way that they can supply output signals of different voltage values to suit the requirements of different processors that may be fitted to the motherboard. The consequence of these different output signal voltage values is that the requirements regarding the transit time differences that can be tolerated with respect to the time delay between the clock signals controlling the processor, and the clock signals controlling the main memory, can no longer be satisfied.
The invention rests, therefore, on the requirement of providing a circuit configuration of the type described in the foregoing which makes it possible that the requirement for an edge-synchronous control of the processor as well as the main memory can also be satisfied even when the voltage values of the output signals supplied by the clock generator change as a result of the need to adapt them to different processors.
According to the invention, this requirement is satisfied in that the input stage contains an amplifier which comprises a circuit component that influences the signal transit time, and that this circuit component is controlled in such a way that it changes the signal transit time in inverse proportion to the changes of the clock generator output signal voltage level.
As a result of the use of this special input stage, the circuit configuration according to the invention ensures that any change of the voltage level of the output signals supplied by the clock generator will not affect the signal transit time, so that, in conjunction with the function of the PLL circuit, the conditions of the edge-synchronicity demanded can be adhered to.